32-bit Superscalar RISC-V CPU
Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs
💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.
Advanced Architecture Labs with CVA6
Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor
Super scalar Processor design
🎞 Implementation of several Branch Prediction algorithms and analysis on their effectiveness on real-world program traces.
Kite: Architecture Simulator for RISC-V Instruction Set
Computer Architecture UIUC SP 2018
A branch predictor simulator in C++ that tests 6 different types of branch predictors.
A MIPS processor with Cache and Advanced Branch Predictor written in SystemVerilog
Two Level Branch Predictor Simulator - EE382N Superscalar Microprocessor Architecture, Spring 2019, Assignment 4
Computer architecture related projects
SystemVerilog implementation of RISC-V RV32IM & custom packed SIMD ISA as 5-stage single-issue CPU core with branch predictor and L1 caches, tied up in lockstep with ISA sim over DPI for verification
Tool for visualizing and comparing different dynamic branch prediction methods for a pipelined processor.
VHDL code of three branch predictors
A 6-Stage RISC-V RV32IM Core on FPGA (263.7 CoreMark, 91.0 DMIPS@100MHz)
C++ Instruction Set Simulator for RISC-V RV32IMC & custom packed SIMD ISA with cache and branch predictor models, C/ASM workloads, and Python analysis tools
This repository contains the code to benchmark CPU cache miss latency and branch misprediction penalty
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